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? semiconductor components industries, llc, 2012 june, 2012 ? rev. 1 1 publication order number: NCP1612/d NCP1612 enhanced, high-efficiency power factor controller the NCP1612 is designed to drive pfc boost stages based on an innovative c urrent c ontrolled f requency f old ? back ( ccff ) method. in this mode, the circuit classically operates in cr itical conduction m ode ( crm ) when the inductor current exceeds a programmable value. when the current is below this preset level, the NCP1612 linearly decays the frequency down to about 20 khz when the current is null. ccff maximizes the efficiency at both nominal and light load. in particular, the stand ? by losses are reduced to a minimum. like in fccrm controllers, an internal circuitry allows near ? unity power factor even when the switching frequency is reduced. housed in a so ? 10 package, the circuit also incorporates the features necessary for robust and compact pfc stages, with few external components. general features ? near ? unity power factor ? critical conduction mode (crm) ? current controlled frequency fold ? back (ccff): low frequency operation is forced at low current levels ? on ? time modulation to maintain a proper current shaping in ccff mode ? skip mode near the line zero crossing ? fast line / load transient compensation (dynamic response enhancer) ? valley turn on ? high drive capability: ? 500 ma/+800 ma ? v cc range: from 9.5 v to 35 v ? low start ? up consumption ? a version: low v cc start ? up level (10.5 v), b version: high v cc start ? up level (17.0 v) ? line range detection ? pfcok signal ? this is a pb ? free device safety features ? separate pin for fast over ? voltage protection (fovp) and bulk under ? voltage detection (buv) ? soft over ? voltage protection ? brown ? out detection ? soft ? start for smooth start ? up operation (a version) ? over current limitation ? disable protection if the feedback and fovp/buv pins are not connected ? thermal shutdown ? latched off capability ? low duty ? cycle operation if the bypass diode is shorted ? open ground pin fault monitoring typical applications ? pc power supplies ? all off line appliances requiring power factor correction soic ? 10 case 751bq pin connections marking diagram (top view) http://onsemi.com 1612x = specific device code x = a or b a = assembly location l = wafer lot y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 29 of this data sheet. ordering information 1 10 1612x alyw 1 10 pfcok v cc drv gnd fovp/buv 1 cs/zcd v control v sense feedback ffcontrol
NCP1612 http://onsemi.com 2 figure 1. typical application schematic maximum ratings table symbol pin rating value unit v cc 9 power supply input ? 0.3, + 35 v v i 1, 2, 4, 5, 10 input voltage (note 1) ? 0.3, +9 v v i(cs/zcd) 6 input voltage ? 0.3, v cl(pos) * v v control 3 v control pin ? 0.3, v control max* v drv 8 driver voltage driver current ? 0.3, v drv * ? 500, +800 v ma p d r ja power dissipation and thermal characteristics maximum power dissipation @ t a = 70 c thermal resistance junction ? to ? air 550 145 mw c/w t j operating junction temperature range ? 40 to +125 c t jmax maximum junction temperature 150 c t smax storage temperature range ? 65 to 150 c t lmax lead temperature (soldering, 10s) 300 c msl moisture sensitivity level 1 ? esd capability, human body model (note 2) > 2000 v esd capability, machine model (note 2) > 200 v esd capability, charged device model (note 2) 2000 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *?v cl(pos) ? is the cs/zcd pin positive clamp voltage. ?v control max? is the v control pin clamp voltage. ?v drv ? is the drv clamp voltage (v drvhigh ) if this clamp voltage is below v cc . ?v drv ? is v cc otherwise. 1. when the applied voltage exceeds 5 v, these pins sink about v 1 5v 4k that is about 1.25 ma if v i = 9 v 2. this device(s) contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22 ? a114e machine model method 200 v per jedec standard jesd22 ? a115 ? a charged device model method 200 v per jedec standard jesd22 ? c101e 3. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
NCP1612 http://onsemi.com 3 typical electrical characteristics (conditions: v cc = 15 v, t j from ? 40 c to +125 c, unless otherwise specified) symbol rating min typ max unit start ? up and supply circuit v cc(on) start ? up threshold, v cc increasing: a version b version 9.75 15.80 10.50 17.00 11.25 18.20 v v cc(off) minimum operating voltage, v cc falling 8.5 9.0 9.5 v v cc(hyst) hysteresis ( v cc ( on ) ? v cc ( off ) ) a version b version 0.75 6.00 1.50 8.00 ? ? v v cc(reset) v cc level below which the circuit resets 2.5 4.0 6.0 v i cc(start) start ? up current, v cc = 9.4 v ? 20 50 a i cc(op)1 operating consumption, no switching (v sense pin being grounded) ? 0.5 1.0 ma i cc(op)2 operating consumption, 50 khz switching, no load on drv pin ? 2.0 3.0 ma current controlled frequency fold ? back t dt1 dead ? time, v ffcontrol = 2.60 v (note 4) ? ? 0 s t dt2 dead ? time, v ffcontrol = 1.75 v 14 18 22 s t dt3 dead ? time, v ffcontrol = 1.00 v 32 38 44 s i dt1 ffcontrol pin current, v sense = 1.4 v and v control maximum 180 200 220 a i dt2 ffcontrol pin current, v sense = 2.8 v and v control maximum 110 135 160 a v skip ? h ffcontrol pin skip level, v ffcontrol rising ? 0.75 0.85 v v skip ? l ffcontrol pin skip level, v ffcontrol falling 0.55 0.65 ? v v skip ? l ffcontrol pin skip hysteresis 50 ? ? mv gate drive t r output voltage rise ? time @ c l = 1 nf, 10 ? 90% of output signal ? 30 ? ns t f output voltage fall ? time @ c l = 1 nf, 10 ? 90% of output signal ? 20 ? ns r oh source resistance ? 10 ? r ol sink resistance ? 7.0 ? i source peak source current, v drv = 0 v (guaranteed by design) ? 500 ? ma i sink peak sink current, v drv = 12 v (guaranteed by design) ? 800 ? ma v drvlow drv pin level at v cc close to v cc ( off ) with a 10 k resistor to gnd 8.0 ? ? v v drvhigh drv pin level at v cc = 35 v ( r l = 33 k , c l = 220 pf) 10 12 14 v regulation block v ref feedback voltage reference: @ 25 c over the temperature range 2.44 2.42 2.50 2.50 2.54 2.54 v i ea error amplifier current capability ? 20 ? a g ea error amplifier gain 110 220 290 s v control ? v control max ? v control min v control pin voltage: ? @ v fb = 2 v ? @ v fb = 3 v ? ? 4.5 0.5 ? ? v v out l / v ref ratio ( v out low detect threshold / v ref ) (guaranteed by design) 95.0 95.5 96.0 % h out l / v ref ratio ( v out low detect hysteresis / v ref ) (guaranteed by design) ? ? 0.5 % i boost v control pin source current when ( v out low detect) is activated 180 220 250 a 4. there is actually a minimum dead ? time that is the delay between the core reset detection and the drv turning on (t zcd parameter of the ?current sense and zero current detection blocks? section).
NCP1612 http://onsemi.com 4 typical electrical characteristics (conditions: v cc = 15 v, t j from ? 40 c to +125 c, unless otherwise specified) symbol unit max typ min rating current sense and zero current detection blocks v cs(th) current sense voltage reference 450 500 550 mv t leb,ocp over ? current protection leading edge blanking time (guaranteed by design) 100 200 350 ns t leb,ovs ?overstress? leading edge blanking time (guaranteed by design) 50 100 170 ns t ocp over ? current protection delay from v cs/zcd > v cs(th) to drv low (d v cs/zcd / d t = 10 v/ s) ? 40 200 ns v zcd(th)h zero current detection, v cs/zcd rising 675 750 825 mv v zcd(th)l zero current detection, v cs/zcd falling 200 250 300 mv v zcd(hyst) hysteresis of the zero current detection comparator 375 500 ? mv r zcd/cs v zcd(th)h over v cs(th) ratio 1.4 1.5 1.6 ? v cl(pos) cs/zcd positive clamp @ i cs/zcd = 5 ma ? 15.6 ? v i zcd(bias) current sourced by the cs/zcd pin, v cs/zcd = v zcd ( th ) h 0.5 ? 2.0 a i zcd(bias) current sourced by the cs/zcd pin, v cs/zcd = v zcd ( th ) l 0.5 ? 2.0 a t zcd ( v cs/zcd < v zcd ( th ) l ) to (drv high) ? 60 200 ns t sync minimum zcd pulse width ? 110 200 ns t wdg watch dog timer 80 200 320 s t wdg(os) watch dog timer in ?overstress? situation 400 800 1200 s t tmo time ? out timer 20 30 50 s i zcd(gnd) source current for cs/zcd pin impedance testing ? 250 ? a static ovp d min duty cycle, v fb = 3 v, v control pin open ? ? 0 % on ? time control t on(ll) maximum on time, v sense = 1.4 v and v control maximum (crm) 22.0 25.0 29.0 s t on(ll)2 on time, v sense = 1.4 v and v control = 2.5 v (crm) 10.5 12.5 14.0 s t on(hl) maximum on time, v sense = 2.8 v and v control maximum (crm) 7.3 8.5 9.6 s t on(ll)(min) minimum on time, v sense = 1.4 v (not tested, guaranteed by characterization) ? ? 200 ns t on(hl)(min) minimum on time, v sense = 2.8 v (not tested, guaranteed by characterization) ? ? 100 ns feed ? back over and under ? voltage protection (soft ovp and uvp) r softovp ratio (soft ovp threshold, v fb rising) over v ref ( v softovp / v ref ) (guaranteed by design) 104 105 106 % r softovp(hyst) ratio (soft ovp hysteresis) over v ref (guaranteed by design) 1.5 2.0 2.5 % r uvp ratio (uvp threshold, v fb rising) over v ref ( v uvp / v ref ) (guaranteed by design) 8 12 16 % r uvp(hyst) ratio (uvp hysteresis) over v ref (guaranteed by design) ? ? 1 % (i b ) fb fb pin bias current @ v fb = v softov p and v fb = v uvp 50 200 450 na fast over voltage protection and bulk under ? voltage protection (fast ovp and buv) v fastovp latching fast ovp threshold, v fovp/buv rising ? 2.7 ? v r fastovp1 ratio (fast ovp threshold, v fovp / buv rising) over (soft ovp threshold, v fb rising) ( v fastovp / v softovp ) (guaranteed by design) 101.5 102.0 102.5 % r fastovp2 ratio (fast ovp threshold, v fovp / buv rising) over v ref ( v fastovp / v ref ) (guaranteed by design) 106 107 108 % v buv buv threshold, v fovp / buv falling ? 1.9 ? v 4. there is actually a minimum dead ? time that is the delay between the core reset detection and the drv turning on (t zcd parameter of the ?current sense and zero current detection blocks? section).
NCP1612 http://onsemi.com 5 typical electrical characteristics (conditions: v cc = 15 v, t j from ? 40 c to +125 c, unless otherwise specified) symbol unit max typ min rating fast over voltage protection and bulk under ? voltage protection (fast ovp and buv) r buv ratio (buv threshold, v fovp / buv falling) over v ref ( v buv / v ref ) (guaranteed by design) 74 76 78 % (i b ) fovp/buv fovp/buv pin bias current @ v fovp / buv = v fastovp and v fovp / buv = v buv 50 200 450 na v uvp2 threshold for floating pin detection 0.2 0.3 0.4 v brown ? out protection and feed ? forward v boh brown ? out threshold, v sense rising 0.96 1.00 1.04 v v bol brown ? out threshold, v sense falling 0.86 0.90 0.94 v v bo(hyst) brown ? out comparator hysteresis 60 100 ? mv t bo(blank) brown ? out blanking time 35 50 65 ms i control(bo) v control pin sink current, v sense < v bol 40 50 60 a v hl high ? line detection comparator threshold, v sense rising 2.1 2.2 2.3 v v ll high ? line detection comparator threshold, v sense falling 1.6 1.7 1.8 v v hl(hyst) high ? line detection comparator hysteresis 400 500 600 mv t hl(blank) blanking time for line range detection 15 25 35 ms i bo(bias) brown ? out pin bias current, v sense = v bo ? 250 ? 250 na pfcok signal (v pfcok ) l pfcok low state voltage @ i pfcok = 5 ma ? ? 250 mv v stdwn shutdown threshold voltage 7.0 7.5 8.0 v r pfcok impedance of the pfcok pin 150 300 ? k thermal shutdown t limit thermal shutdown threshold ? 150 ? c h temp thermal shutdown hysteresis ? 50 ? c 4. there is a ctually a minimum dead ? time that is the delay between the core reset detection and the drv turning on (t zcd parameter of the ?current sense and zero current detection blocks? section). detailed pin description pin number name function 1 fovp / buv v pin1 is the input signal for the fast over ? voltage (fovp) and bulk under ? voltage (buv) comparators. the circuit disables the driver if v pin1 exceeds the fovp threshold which is set 2% higher than the reference for the soft ovp comparator (that monitors the feedback pin) so that pins 1 and 2 can receive the same portion of the output voltage. the buv comparator trips when v pin 1 drops below 76% of the 2.5 v reference voltage to disable the driver and ground the pfcok pin. the buv function has no action whenever the pfcok pin is in low state. as a matter of fact, pin1 monitors the output voltage and checks if it is high enough for proper operation of the downstream converter. a 250 na sink current is built ? in to ground the pin and disable the driver if the pin is accidentally open. 2 feedback this pin receives a portion of the pfc output voltage for the regulation and the dynamic response enhancer (dre) that drastically speeds ? up the loop response when the output voltage drops below 95.5% of the desired output level. v pin2 is also the input signal for the over ? voltage (ovp) and under ? voltage (uvp) comparators. the uvp comparator prevents operation as long as v pin2 is lower than 12% of the reference voltage (v ref ). a soft ovp comparator gradually reduces the duty ? ratio to zero when v pin2 exceeds 105% of v ref (soft ovp). a 250 a sink current is built ? in to trigger the uvp protection and disable the part if the feedback pin is accidentally open.
NCP1612 http://onsemi.com 6 detailed pin description pin number function name 3 v control the error amplifier output is available on this pin. the network connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 hz to achieve high power factor ratios. pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly to provide a soft ? start function. 4 v sense a portion of the instantaneous input voltage is to be applied to pin4 in order to detect brown ? out conditions. if v pin 4 is lower than 1 v for more than 50 ms, the circuit stops pulsing until the pin voltage rises again and exceeds 1 v. this pin also detects the line range. by default, the circuit operates the ?low ? line gain? mode. if v pin 4 exceeds 1.8 v, the circuit detects a high ? line condition and reduces the loop gain by 3. conversely, if the pin voltage remains lower than 1.8 v for more than 25 ms, the low ? line gain is set. connecting the pin 4 to ground disables the part. 5 ff control this pin sources a current representative to the line current. connect a resistor between pin5 and ground to generate a voltage representative of the line current. when this voltage exceeds the internal 2.5 v reference ( v ref ), the circuit operates in critical conduction mode. if the pin voltage is below 2.5 v, a dead ? time is generated that approximately equates [83 s ? (1 ? (v pin5 /v ref ))]. by this means, the circuit forces a longer dead ? time when the current is small and a shorter one as the current increases. the circuit skips cycles whenever v pin 5 is below 0.65 v to prevent the pfc stage from operating near the line zero crossing where the power transfer is particularly inefficient. this does result in a slightly increased distortion of the current. if superior power factor is required, offset pin 5 by more than 0.75 v offset to inhibit the skip function. 6 cs / zcd this pin monitors the mosfet current to limit its maximum current. this pin is also connected to an internal comparator for zero current detection (zcd). this comparator is designed to monitor a signal from an auxiliary winding and to detect the core reset when this voltage drops to zero. the auxiliary winding voltage is to be applied through a diode to avoid altering the current sense information for the on ? time (see application schematic). 7 ground connect this pin to the pfc stage ground. 8 drive the high ? current capability of the totem pole gate drive ( ? 0.5/+0.8 a) makes it suitable to effectively drive high gate charge power mosfets. 9 v cc this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 10.5 v (a version, 17.0 v for the b version) and turns off when v cc goes below 9.0 v (typical values). after start ? up, the operating range is 9.5 v up to 35 v. 10 pfcok this pin is grounded until the pfc output has reached its nominal level. it is also grounded if the NCP1612 detects a fault. for the rest of the time, i.e., when the pfc stage outputs the nominal bulk voltage, pin10 is in high ? impedance state. this circuit latches off if pin10 exceeds 7.5 v.
NCP1612 http://onsemi.com 7 figure 2. block diagram
NCP1612 http://onsemi.com 8 typical characteristics figure 3. start ? up threshold, v cc increasing (v cc(on) ) vs. temperature (a version) figure 4. start ? up threshold, v cc increasing (v cc(on) ) vs. temperature (b version) t j , junction temperature ( c) t j , junction temperature ( c) 110 90 70 30 10 ? 10 ? 30 ? 50 9.0 9.5 10.0 10.5 11.0 11.5 12.0 110 90 70 30 10 ? 10 ? 30 ? 50 16.0 16.2 16.6 16.8 17.0 17.2 17.4 17.6 figure 5. v cc minimum operating voltage, v cc falling (v cc(off) ) vs. temperature figure 6. hysteresis (v cc(on) ? v cc(off) ) vs. temperature (a version) t j , junction temperature ( c) t j , junction temperature ( c) 8.00 8.25 8.50 8.75 9.00 9.50 9.75 10.00 0.50 0.75 1.00 1.25 1.50 1.75 2.00 figure 7. start ? up current @ v cc = 9.4 v vs. temperature figure 8. operating current, no switching (v sense grounded) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0 10 20 30 40 50 60 70 0 0.25 0.50 0.75 1.00 1.25 1.50 v cc(on) (v) v cc(on) (v) v cc(off) (v) v cc(hysr) (v) i cc(start) ( a) i cc(0p)1 (ma) 50 130 50 130 16.4 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 9.25 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 9 typical characteristics figure 9. ffcontrol pin current, v sense = 1.4 v and v control maximum vs. temperature figure 10. ffcontrol pin current, v sense = 2.8 v and v control maximum vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 125 150 175 225 250 275 300 50 75 100 125 150 175 200 figure 11. dead ? time, v ffcontrol = 1.75 v vs. temperature figure 12. dead ? time, v ffcontrol = 1.00 v vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 12.5 14.5 16.5 18.5 20.5 22.5 35 36 37 38 39 40 figure 13. ffcontrol pin skip level (v ffcontrol rising) vs. temperature figure 14. ffcontrol pin skip level (v ffcontrol falling) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.45 0.55 0.65 0.75 0.85 i dt1 ( a) i dt2 ( a) t dt2 ( s) t dt3 ( s) v skip ? h (v) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 200 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 0.45 0.55 0.65 0.75 0.85 v skip ? l (v) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 10 typical characteristics figure 15. drv source resistance vs. temperature figure 16. drv voltage rise ? time (c l = 1 nf, 10 ? 90% of output signal) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0 5 10 15 20 25 figure 17. drv sink resistance vs. temperature figure 18. drv voltage fall ? time (c l = 1 nf, 10 ? 90% of output signal) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 19. drv pin level @ v cc = 35 v (r l = 33 k , c l = 1 nf) vs. temperature figure 20. feedback reference voltage vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0 4 8 12 16 20 2.35 2.40 2.45 2.50 2.55 2.60 2.65 r oh ( ) t rise (ns) r ol ( ) t fall (ns) v drvhigh (v) v ref (v) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 0 10 20 30 40 50 60 70 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 0 5 10 15 20 25 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 0 10 20 30 40 50 60 70 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 11 typical characteristics figure 21. error amplifier transconductance gain vs. temperature figure 22. ratio (v out low detect threshold / v ref ) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 150 175 200 225 250 93 94 95 96 97 98 figure 23. ratio (v out low detect hysteresis / v ref ) vs. temperature figure 24. v control source current when (v out low detect) is activated for dynamic response enhancer (dre) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0 0.1 0.2 0.3 0.4 0.5 140 160 180 200 220 240 260 280 figure 25. current sense voltage threshold vs. temperature figure 26. over ? current protection leading edge blanking vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 480 485 490 495 505 510 515 520 120 140 160 180 220 240 260 280 g ea ( s) v out l / v ref (%) h out l / v ref (%) i boost ( a) v bcs(th) (mv) t leb ? ocp (ns) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 500 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 200
NCP1612 http://onsemi.com 12 typical characteristics figure 27. ?overstress? protection leading edge blanking vs. temperature figure 28. over ? current protection delay from v cs/zcd > v cs(th) to drv low (dv cs/zcd / dt = 10 v/ s) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 60 70 80 100 110 120 130 140 0 20 40 60 80 100 figure 29. zero current detection, v cs/zcd rising vs. temperature figure 30. zero current detection, v cs/zcd falling vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 650 700 750 800 850 230 235 240 245 255 260 265 270 figure 31. hysteresis of the zero current detection comparator vs. temperature figure 32. v zcd(th) over v cs(th) ratio vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 420 440 460 480 500 520 540 560 1.2 1.3 1.4 1.5 1.6 1.7 1.8 t leb ? ovs (ns) t ocp (ns) v zcd(th)h (mv) v zcd(th)l (mv) v zcd(hyst) (mv) r zcd/cs ( ? ) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 90 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 250 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 13 typical characteristics figure 33. cs/zcd pin bias current @ v cs/zcd = 0.75 v vs. temperature figure 34. watchdog timer vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.5 0.6 0.8 0.9 1.1 1.2 1.4 1.5 160 170 180 190 210 220 230 240 figure 35. watchdog timer in ?overstress? situation vs. temperature figure 36. minimum zcd pulse width for zcd detection vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 640 680 720 760 840 880 920 960 80 90 100 110 120 130 140 figure 37. ((v cs/zcd < v zcd(th) ) to drv high) delay vs. temperature figure 38. timeout timer vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 40 50 60 70 80 90 100 110 28 29 30 31 32 i zcd/(bias) ( a) t wtg ( s) t wtg(os) ( s) t sync (ns) t zcd (ns) t tmo ( s) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 0.7 1.0 1.3 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 200 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 800 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 14 typical characteristics figure 39. maximum on time @ v sense = 1.4 v vs. temperature figure 40. maximum on time @ v sense = 2.8 v vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 24.0 24.5 25.0 25.5 26.0 26.5 27.0 8.2 8.3 8.4 8.5 8.6 8.7 8.8 figure 41. minimum on time @ v sense = 1.4 v vs. temperature figure 42. minimum on time @ v sense = 2.8 v vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 20 30 40 50 60 80 90 100 figure 43. ratio (soft ovp threshold, v fb rising) over v ref vs. temperature figure 44. ratio (soft ovp hysteresis) over v ref vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 104.6 104.7 104.8 104.9 105.0 105.2 105.3 105.4 1.8 1.9 2.0 2.1 2.2 t on(ll) ( s) t on(hl) ( s) t on(ll)(min) (ns) t on(hl)(min) (ns) r softovp (%) r softovp(hyst) (%) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 70 20 30 40 50 60 80 90 100 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 70 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 105.1 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 15 typical characteristics figure 45. ratio (fastovp threshold, v fovp/buv rising) over v ref vs. temperature figure 46. feedback pin bias current @ v fb = v ovp vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 106.6 106.7 106.8 106.9 107.1 107.2 107.3 107.4 150 170 190 210 230 250 270 290 figure 47. feedback pin bias current @ v fb = v uvp vs. temperature figure 48. ratio (uvp threshold, v fb rising) over v ref vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 150 170 190 210 230 250 270 290 9 10 11 12 13 14 15 figure 49. ratio (uvp hysteresis) over v ref vs. temperature figure 50. brown ? out threshold, v sense rising vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90 0.95 1.00 1.05 1.10 r fastovp2 (%) i b(fb) (na) i b(fb)2 (na) r fuvp (%) r fuvp(hyst) (%) v boh (v) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 107.0 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 16 typical characteristics figure 51. brown ? out threshold, v sense falling vs. temperature figure 52. brown ? out comparator hysteresis vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.80 0.85 0.90 0.95 1.00 90 95 100 105 110 figure 53. brown ? out blanking time vs. temperature figure 54. v control pin sink current when a brown ? out situation is detected vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 40 45 50 55 60 40 45 50 55 60 figure 55. comparator threshold for line range detection, v sense rising vs. temperature figure 56. comparator threshold for line range detection, v sense falling vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 1.9 2.0 2.1 2.2 2.3 2.4 1.5 1.6 1.7 1.8 1.9 v bol (v) v bo(hyst) (mv) t bo(blank) (ms) i control(bo) ( a) v hl (v) v ll (v) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130
NCP1612 http://onsemi.com 17 typical characteristics figure 57. blanking time for line range detection vs. temperature figure 58. brown ? out pin bias current, (v sense = v boh ) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 20 22 24 26 28 30 ? 4 ? 2 ? 1 1 3 5 6 8 t hl(blank) (ms) i bo(bias) (na) 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 110 90 70 30 10 ? 10 ? 30 ? 50 50 130 ? 3 0 2 4 7 detailed operating description introduction the NCP1612 is designed to optimize the efficiency of your pfc stage throughout the load range. in addition, it incorporates protection features for rugged operation. more generally, the NCP1612 is ideal in systems where cost ? effectiveness, reliability, low stand ? by power and high efficiency are the key requirements: ? current controlled frequency fold ? back: the NCP1612 is designed to drive pfc boost stages in so ? called current controlled frequency fold ? back (ccff). in this mode, the circuit classically operates in critical conduction mode (crm) when the inductor current exceeds a programmable value. when the current is below this preset level, the NCP1612 linearly reduces the frequency down to about 20 khz when the current is zero. ccff maximizes the efficiency at both nominal and light load. in particular, stand ? by losses are reduced to a minimum. similarly to fccrm controllers, an internal circuitry allows near ? unity power factor even when the switching frequency is reduced. ? skip mode: to further optimize the efficiency, the circuit skips cycles near the line zero crossing when the current is very low. this is to avoid circuit operation when the power transfer is particularly inefficient at the cost of current distortion. when superior power factor is required, this function can be inhibited by offsetting the ?ffcontrol? pin by 0.75 v. ? low start ? up current and large v cc range (b version): the consumption of the circuit is minimized to allow the use of high ? impedance start ? up resistors to pre ? charge the v cc capacitor. also, the minimum value of the uvlo hysteresis is 6 v to avoid the need for large v cc capacitors and help shorten the start ? up time without the need for too dissipative start ? up elements. the a version is preferred in applications where the circuit is fed by an external power source (from an auxiliary power supply or from a downstream converter). its maximum start ? up level (11.25 v) is set low enough so that the circuit can be powered from a 12 v rail. after start ? up, the high v cc maximum rating allows a large operating range from 9.5 v up to 35 v. ? pfcok signal: the pfcok pin is to disable/enable the downstream converter. grounded until the pfc output has reached its nominal level and whenever the NCP1612 detects a fault, it is in high ? impedance when the pfc stage outputs the nominal bulk voltage. in addition, the circuit latches off if a voltage exceeding 7.5 v is applied to pin 10. ? fast line / load transient compensation (dynamic response enhancer): since pfc stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start ? up) may cause excessive over or under ? shoot. this circuit limits possible deviations from the regulation level as follows: ? the soft and fast over voltage protections firmly contains the output voltage when it tends to become excessive. ? the NCP1612 dramatically speeds ? up the regulation loop when the output voltage goes below 95.5 % of its regulation level. this function is enabled only after the pfc stage has started ? up not to eliminate the soft ? start effect. ? safety protections: the NCP1612 permanently monitors the input and output voltages, the mosfet current and the die temperature to protect the system from possible over ? stress making the pfc stage extremely robust and
NCP1612 http://onsemi.com 18 reliable. in addition to the ovp protection, these methods of protection are provided: ? maximum current limit: the circuit senses the mosfet current and turns off the power switch if the set current limit is exceeded. in addition, the circuit enters a low duty ? cycle operation mode when the current reaches 150% of the current limit as a result of the inductor saturation or a short of the bypass diode. ? under ? voltage protection: this circuit turns off when it detects that the output voltage is below 12% of the voltage reference (typically). this feature protects the pfc stage if the ac line is too low or if there is a failure in the feedback network (e.g., bad connection). ? detection of the output voltage improper level: the ?fovp/buv? monitors the output voltage. typically, the same portion of the output voltage is applied as to the feedback pin. the circuit disables the driver if the pin 1 voltage exceeds 102% of the soft ovp threshold. the circuit also monitors the output voltage to detect when the pfc stage cannot maintain the bulk voltage at a high enough level (buv situation). when the buv function trips, the ?pfcok? pin is grounded, to disable the downstream converter. ? brown ? out detection: the circuit detects low ac line conditions and stops operation thus protecting the pfc stage from excessive stress. ? thermal shutdown: an internal thermal circuitry disables the gate drive when the junction temperature exceeds 150 c (typically). the circuit resumes operation once the temperature drops below approximately 100 c (50 c hysteresis). ? output stage totem pole: the NCP1612 incorporates a ? 0.5 a / +0.8 a gate driver to efficiently drive most to220 or to247 power mosfets. NCP1612 operation modes as mentioned, the NCP1612 pfc controller implements a c urrent c ontrolled f requency f old ? back ( ccff ) where: ? the circuit operates in classical cr itical conduction m ode ( crm ) when the inductor current exceeds a programmable value. ? when the current is below this preset level, the NCP1612 linearly reduces the operating frequency down to about 20 khz when the current is zero. high current no delay crm low current the next cycle is delayed lower current longer dead ? time timer delay timer delay high current no delay crm low current the next cycle is delayed lower current longer dead ? time timer delay timer delay figure 59. ccff operation as illustrated in figure 59, under high load conditions, the boost stage is operating in crm but as the load is reduced, the controller enters controlled frequency discontinuous operation. figure 60 details the operation. a voltage representative of the input current (?current information?) is generated. if this signal is higher than a 2.5 v internal reference (named ?dead ? time ramp threshold? in figure 60), there is no dead ? time and the circuit operates in crm. if the current information is lower than the 2.5 v threshold, a dead ? time is inserted that lasts for the time necessary for the internal ramp to reach 2.5 v from the current information floor. hence, the lower the current information is, the longer the dead ? time. when the current information is 0.75 v, the dead ? time is 50 s. to further reduce the losses, the mosfet turns on is stretched until its drain ? source voltage is at its valley. as illustrated in figure 60, the ramp is synchronized to the drain ? source ringing. if the ramp exceeds the 2.5 v threshold while the drain ? source voltage is below v in , the ramp is extended until it oscillates above v in so that the drive will turn on at the next valley.
NCP1612 http://onsemi.com 19 top: crm operation when the current information exceeds the preset level during the demagnetization phase middle: the circuit re ? starts at the next valley if the sum (ramp + current information) exceeds the preset level during the dead ? time, while the drain ? source voltage is high bottom: the sum (ramp + current information) exceeds the preset level while during the dead ? time, the drain ? source voltage is low. the circuit skips the current valley and re ? starts at the following one. figure 60. dead ? time generation
NCP1612 http://onsemi.com 20 current information generation the ?ffcontrol? pin sources a current that is representative of the input current. in practice, i pin 5 is built by multiplying the internal control signal ( v regul , i.e., the internal signal that controls the on ? time) by the sense voltage (pin 4) that is proportional to the input voltage. the multiplier gain ( k m of figure 61) is three times less in high ? line conditions (that is when the ??lline? signal from the brown ? out block is in low state) so that i pin 5 provides a voltage representative of the input current across resistor r ff placed between pin 5 and ground. pin 5 voltage is the current information. bo pin v to i converter vcontrol pin v to i converter multiplier ffcontrol pin sum ramp 1v skip2 pfcok i bo i regul i bo i regul k m . i regul . i bo i regul = k . v regul r ff + lline v sense pin v control pin ffcontrol pin 0.75 v / 0.65 v skip ramp sum pfcok figure 61. generation of the current information skip mode as illustrated in figure 61, the circuit also skips cycles near the line zero crossing where the current is very low. a comparator monitors the pin 5 voltage (?ffcontrol? voltage) and inhibits the switching operation when v pin 5 is lower than a 0.65 v internal reference. switching resumes when v pin 5 exceeds 0.75 v (0.1 v hysteresis). this function prevents circuit operation when the power transfer is particularly inefficient at the expense of slightly increased current distortion. when superior power factor is needed, this function can be inhibited of fsetting the ?ffcontrol? pin by 0.75 v. the skip mode capability is disabled whenever the pfc stage is not in nominal operation (as dictated by the ?pfcok? signal ? see block diagram and ?pfcok internal signal? section). the circuit does not abruptly interrupt the switching when v pin 5 goes below 0.65 v. instead, the signal v ton that controls the on ? time is gradually decreased by grounding the v regul signal applied to the v ton processing block (see figure 66). doing so, the on ? time smoothly decays to zero in 3 to 4 switching periods typically. figure 62 shows the practical implementation.
NCP1612 http://onsemi.com 21 figure 62. ccff practical implementation ccff maximi zes the efficiency at both nominal and light load. in particular, the stand ? by losses are reduced to a minimum. also, this method avoids that the system stalls between valleys. instead, the circuit acts so that the pfc stage transitions from the n valley to (n + 1) valley or vice versa from the n valley to (n ? 1) cleanly as illustrated by figure 63. figure 63. clean transition without hesitation between valleys
NCP1612 http://onsemi.com 22 NCP1612 on ? time modulation let?s analyze the ac line current absorbed by the pfc boost stage. the initial inductor current at the beginning of each switching cycle is always zero. the coil current ramps up when the mosfet is on . the slope is ( v in / l ) where l is the coil inductance. at the end of the on ? time ( t 1 ), the inductor starts to demagnetize. the inductor current ramps down until it reaches zero. the duration of this phase is ( t 2 ). in some cases, the system enters then the dead ? time ( t 3 ) that lasts until the next clock is generated. one can show that the ac line current is given by: i in v in t 1 t 1 t 2 2tl (eq. 1) where t = ( t 1 + t 2 + t 3 ) is the switching period and v in is the ac line rectified voltage. in light of this equation, we immediately note that i in is proportional to v in if [ t 1 ( t 1 + t 2 ) / t ] is a constant. figure 64. pfc boost converter (left) and inductor current in dcm (right) the NCP1612 operates in voltage mode. as portrayed by figure 65, the mosfet on ? time t 1 is controlled by the signal v ton generated by the regulation block and an internal ramp as follows: t 1 c ramp v ton i ch (eq. 2) the charge current is constant at a given input voltage (as mentioned, it is three times higher at high line compared to its value at low line). c ramp is an internal capacitor. the output of the regulation block (v control ) is linearly transformed into a signal (v regul ) varying between 0 and 1 v. ( v regu l ) is the voltage that is injected into the pwm section to modulate the mosfet duty ? cycle. the NCP1612 includes some circuitry that processes ( v regul ) to form the signal (v ton ) that is used in the pwm section (see figure 66). (v ton ) is modulated in response to the dead ? time sensed during the precedent current cycles, that is, for a proper shaping of the ac line current. this modulation leads to: v ton t v regul t 1 t 2 (eq. 3) or v ton t 1 t 2 t v regul given the low regulation bandwidth of the pfc systems, ( v control ) and then ( v regul ) are slow varying signals. hence, the (v ton ? (t 1 + t 2 )/t) term is substantially constant. provided that in addition, ( t 1 ) is proportional to ( v ton ), equation 1 leads to: , where k is a constant. more exactly: i in k v in where : k constant 1 2l v regul v regul max t on,max where t on , max is the maximum on ? time obtained when v regul is at its ( v regul ) max maximum level. the parametric table shows that t on , max is equal to 25 s (t on(ll) ) at low line and to 8.5 s (t on(hl) ) at high line (when pin4 happens to exceeds 1.8 v with a pace higher than 40 hz ? see bo 25 ms blanking time). hence, we can re ? write the above equation as follows: i in v in t on(ll) 2 l v regul v regul max at low line. i in v in t on(hl) 2 l v regul v regul max at high line. from these equations, we can deduce the expression of the average input power: p in,avg v in,rms 2 v regul t on(ll) 2 l v regul max at low line
NCP1612 http://onsemi.com 23 p in,avg v in,rms 2 v regul t on(hl) 2 l v regul max at high line where (v regul ) max is the v regul maximum value. hence, the maximum power that can be delivered by the pfc stage is: p in,avg max v in,rms 2 t on(ll) 2 l at low line p in,avg max v in,rms 2 t on(hl) 2 l at high line the input current is then proportional to the input voltage. hence, the ac line current is properly shaped. one can note that this analysis is also valid in the crm case. this condition is just a particular case of this functioning where ( t 3 = 0), which leads to ( t 1 + t 2 = t ) and (v ton = v regul ). that is why the NCP1612 automatically adapts to the conditions and transitions from dcm and crm (and vice versa) without power factor degradation and without discontinuity in the power delivery. figure 65. pwm circuit and timing diagram. figure 66. v ton processing circuit. the integrator oa1 amplifies the error between v regul and in1 so that on average, (v ton * (t 1 +t 2 )/t) equates v regul . remark: the ? v ton processing circuit? is ?informed? when a condition possibly leading to a long interruption of the drive activity (functions generating the stop signal that disables the drive ? see block diagram ? except ocp, i.e., buv_fault, ovp, overstress, skip, staticovp and off). otherwise, such situations would be viewed as a normal dead ? time phase and v ton would inappropriately over ? dimension v ton to compensate it. instead, as illustrated in figure 66, the v ton signal is grounded leading to a short soft ? start when the circuit recovers.
NCP1612 http://onsemi.com 24 regulation block and low output voltage detection a trans ? conductance error amplifier (ota) with access to the inverting input and output is provided. it features a typical trans ? conductance gain of 200 s and a maximum capability of 20 a. the output voltage of the pfc stage is typically scaled down by a resistors divider and monitored by the inverting input (pin 2). bias current is minimized (less than 500 na) to allow the use of a high impedance feed ? back network. however, it is high enough so that the pin remains in low state if the pin is not connected. the output of the error amplifier is brought to pin 3 for external loop compensation. typically a type ? 2 network is applied between pin 3 and ground, to set the regulation bandwidth below about 20 hz and to provide a decent phase boost. the swing of the error amplifier output is limited within an accurate range: ? it is forced above a voltage drop ( v f ) by some circuitry. ? it is clamped not to exceed 4.0 v + the same v f voltage drop. hence, v pin 3 features a 4 v voltage swing. v pin 3 is then offset down by ( v f ) and scaled down by a resistors divider before it connects to the ? v ton processing block? and the pwm section. finally, the output of the regulation block is a signal (? v regul ? of the block diagram) that varies between 0 and a top value corresponding to the maximum on ? time. the v f value is 0.5 v typically. ( v regul ) max v regul v control figure 67. a) regulation block figure (left), b) correspondence between v control and v regul (right) given the low bandwidth of the regulation loop, abrupt variations of the load, may result in excessive over or under ? shoots. over ? shoot is limited by the soft over ? voltage protection (ovp) connected to the feedback pin or the fast ovp of pin1. the NCP1612 embeds a ?dynamic response enhancer? circuitry (dre) that contains under ? shoots. an internal comparator monitors the feed ? back (v pin1 ) and when v pin2 is lower than 95.5% of its nominal value, it connects a 200 a current source to speed ? up the charge of the compensation network. effectively this appears as a 10x increase in the loop gain. in a version, dre is disabled during the start ? up sequence until the pfc stage has stabilized (that is when the ? pfcok ? signal of the block diagram, is high). the resulting slow and gradual charge of the pin 3 voltage ( v control ) softens the soft start ? up sequence. in b version, dre is enabled during start ? up to speed ? up this phase and allow for the use of smaller v cc capacitors. the circuit also detects overshoot and immediately reduces the power delivery when the output voltage exceeds 105% of its desired level. the NCP1612 does not abruptly interrupt the switching. instead, the signal v ton that controls the on ? time is gradually decreased by grounding the v regul signal applied to the v ton processing block (see figure 66). doing so, the on ? time smoothly decays to zero in 4 to 5 switching periods typically. if the output voltage still increases, the fast ovp comparator immediately disables the driver if the output voltage exceeds 108.5% of its desired level. the error amplifier ota and the soft ovp, uvp and dre comparators share the same input information. based on the typical value of their parameters and if (v out,nom ) is the output voltage nominal value (e.g., 390 v), we can deduce: ? output regulation level : v out,nom ? output soft ovp level : v out,sovp = 105% x v out,nom ? output uvp level : v out,uvp = 12% x v out,nom
NCP1612 http://onsemi.com 25 ? output dre level : v out,dre = 95.5% x v out,nom fast ovp and bulk under ? voltage (buv) these functions check that the output voltage is within the proper window: ? the fast over ? voltage protection trips if the bulk voltage reaches abnormal levels. when the feedback network is properly designed and correctly connected, the bulk voltage cannot exceed the level set by the soft ovp function (v out,sovp = 105% x v out,nom , see precedent section). this second protection offers some redundancy for a higher safety level. the fovp threshold is set 2% higher than the soft ovp comparator reference so that the same portion of the output voltage can be applied to both the fovp/buv and feedback input pins (pins 1 and 2). ? the buv comparator trips when v pin 1 drops below 76% of the 2.5 v reference voltage (vbuv = 76% x vref). in the case, the circuit grounds the pfcok pin (to disable the downstream converter) and gradually discharges the v control signal until the skip level is obtained (see block diagram) so that the next start ? up sequence will be performed with a soft ? start. the drive output is disabled for the v control discharge time. when the v control discharge is complete, the circuit can attempt to recover operation. however, the buv function has no action whenever the pfcok pin is in low state, not to inappropriately interrupt start ? up phases. figure 68. bulk under ? voltage detection as a matter of fact, pin1 monitors the output voltage and checks if it is within the window for proper operation. assuming that the same portion of the output voltage is applied to fovp/buv and feedback pins: ? output fast ovp level: v out,fovp = 107% x v out,nom ? output buv level: v out,buv = 76% x v out,nom hence, if the output regulation voltage is 390 v, the fovp and buv output voltage levels are 417 and 296 v respectively. a 250 na sink current is built ? in to ground the pin if the fovp / buv pin is accidently open. the circuit disables the drive as long as the pin voltage is below 300 mv (typically). current sense and zero current detection the NCP1612 is designed to monitor the current flowing through the power switch. a current sense resistor (r sense ) is inserted between the mosfet source and ground to generate a positive voltage proportional to the mosfet current (v cs ). the v cs voltage is compared to a 500 mv internally reference. when v cs exceeds this threshold, the ocp signal turns high to reset the pwm latch and forces the driver low. a 200 ns blanking time prevents the ocp comparator from tripping because of the switching spikes that occur when the mosfet turns on. the cs pin is also designed to receive a signal from an auxiliary winding for zero current detection. as illustrated in figure 69, an internal zcd comparator monitors the pin6 voltage and if this voltage exceeds 750 mv, a demagnetization phase is detected (signal zcd is high). the auxiliary winding voltage is applied thought a diode to prevent this signal from distorting the current sense information during the on ? time. thus, the ocp protection is not impacted by the zcd sensing circuitry. this
NCP1612 http://onsemi.com 26 comparator incorporates a 500 mv hysteresis and is able to detect zcd pulses longer than 200 ns. when pin 6 voltage drops below the lower zcd threshold, the driver can turn high within 200 ns. it may happen that the mosfet turns on while a huge current flows through the inductor. as an example such a situation can occur at start ? up when large in ? rush currents charge the bulk capacitor to the line peak voltage. traditionally, a bypass diode is generally placed between the input and output high ? voltage rails to divert this inrush current. if this diode is accidentally shorted, the mosfet will also see a high current when it turns on. in both cases, the current can be large enough to trigger the zcd comparator. an and gate detects that this event occurs while the drive signal is high. in this case, a latch is set and the ?overstress? signal goes high and disables the driver for a 800 s delay. this long delay leads to a very low duty ? cycle operation in case of ?overstress? fault in order to limit the risk of overheating. figure 69. current sense and zero current detection blocks when no signal is received that triggers the zcd comparator during the off ? time, an internal 200 s watchdog timer initiates the next drive pulse. at the end of this delay, the circuit senses the cs/zcd pin impedance to detect a possible grounding of this pin and prevent operation. the cs/zcd external components must be selected to avoid false fault detection. 3.9 k is the recommended minimum impedance to be applied to the cs/zcd pin when considering the NCP1612 parameters tolerance over the ? 40 c to 125 c temperature range. practically, r cs must be higher than 3.9 k in the application of figure 69 . pfcok signal the pfcok pin is in high ? impedance state when the pfc stage operates nominally and is grounded in the following cases: ? during the pfc stage start ? up, that is, until the output voltage has stabilized at the right level. ? if the output voltage is too low for proper operation of the downstream converter, more specifically, when the ?buv_fault? signal (see figure 2) is in high state. ? in the case of a condition preventing the circuit from operating properly like in a brown ? out situation or when one of the following faults turns off the circuit: ? incorrect feeding of the circuit (?uvlo? high when v cc < v cc ( off ) , v cc ( off ) equating 9 v typically). ? excessive die temperature detected by the thermal shutdown. ? under ? voltage protection ? latched ? off of the part ? regulation loop failure (uvp) ? brown ? out situation (bo_fault high ? see figure 2) the pfcok signal is controlled as illustrated by figure 70. the circuit monitors the current sourced by the ota. if there is no current, we can deduce that the output voltage has reached its nominal level. the start ? up phase is then complete and pfcok remains high ? impedance until a fault is detected. upon startup, the internal signals and the internal supply rails need some time to stabilize. the pfcok latch cannot be set during this time and until a sufficient blanking time has elapsed. for the sake of simplicity, this blanking delay is not represented in figure 70. another mandatory condition to set pfcok high is the low state of the ?buvcomp? signal. this second necessary condition ensures that the voltage applied to pin 1 is high enough not to immediately trigger the buv protection. the pfcok pin is to be used to enable the downstream converter.
NCP1612 http://onsemi.com 27 figure 70. pfcok detection the circuit also incorporates a comparator to a 7.5 v threshold so that the part latches off if the pfcok pin voltage exceeds 7.5 v. this pin is to protect the part in presence of a major fault like a die over ? heating. to recover operation, a brown ? out condition must be detected (if circuit v cc is properly fed) or v cc must drop below v cc ( reset ) . brown ? out detection the v sense pin (pin4) receives a portion of the instantaneous input voltage ( v in ). as v in is a rectified sinusoid, the monitored signal varies between zero or a small voltage and a peak value. for the brown ? out block, we need to ensure that the line magnitude is high enough for operation. this is done as follows: ? the v sense pin voltage is compared to a 1 v reference. ? if v pin 4 exceeds 1 v, the input voltage is considered sufficient ? if v pin 4 remains below 0.9 v for 50 ms, the circuit detects a brown ? out situation (100 mv hysteresis). by default, when the circuit starts operation, the circuit is in a fault state (?bo_nok? high) until v pin 4 exceeds 1 v. when ?bo_nok? is high, the drive is not disabled. instead, a 50 a current source is applied to pin3 to gradually reduce v control . as a result, the circuit only stops pulsing when the skip function is activated ( v control reaches the skip detection threshold). at that moment, the circuit turns off (see figure 2). this method limits any risk of false triggering. the input of the pfc stage has some impedance that leads to some sag of the input voltage when the drawn current is large. if the pfc stage stops while a high current is absorbed from the mains, the abrupt decay of the current may make the input voltage rise and the circuit detect a correct line level. instead, the gradual decrease of v control avoids a line current discontinuity and limits risk of false triggering. pin4 is also used to sense the line for feed ? forward. a similar method is used: ? the v sense pin voltage is compared to a 2.2 v reference. ? if v pin 4 exceeds 2.2 v, the circuit detects a high ? line condition and the loop gain is divided by three (the internal pwm ramp slope is three times steeper) ? once this occurs, if v pin 4 remains below 1.7 v for 25 ms, the circuit detects a low ? line situation (500 mv hysteresis). at startup, the circuit is in low ? line state (?lline? high?) until v pin 4 exceeds 2.2 v. the line range detection circuit allows more optimal loop gain control for universal (wide input mains) applications. as portrayed in figure 71, the pin 4 voltage is also utilized to generate the current information required for the frequency fold ? back function.
NCP1612 http://onsemi.com 28 figure 71. input line sense monitoring thermal shutdown (tsd) an internal thermal circuitry disables the circuit gate drive and keeps the power switch off when the junction temperature exceeds 150 c. the output stage is then enabled once the temperature drops below about 100 c (50 c hysteresis). the temperature shutdown remains active as long as the circuit is not reset, that is, as long as v cc is higher than v cc ( reset ) . the reset action forces the tsd threshold to be the upper one (150 c), thus ensuring that any cold start ? up will be done with the proper tsd level. output drive section the output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. the gate drive is kept in a sinking mode whenever the under ? voltage lockout is active or more generally whenever the circuit is off. its high current capability ( ? 500 ma/+800 ma) allows it to effectively drive high gate charge power mosfet. as the circuit exhibits a large v cc range (up to 35 v), the drive pin voltage is clamped not to provide the mosfet gate with more than 14 v. reference section the circuit features an accurate internal 2.5 v reference voltage ( v ref ) optimized to be 2.4% accurate over the temperature range. off mode as previously mentioned, the circuit turns off when one of the following faults is detected: ? incorrect feeding of the circuit (?uvlo? high when v cc < v cc ( off ) , v cc ( off ) equating 9 v typically). ? excessive die temperature detected by the thermal shutdown. ? brown ? out fault and skip (see block diagram) ? output under ? voltage situation ( v pin 1 and/or v pin 2 lower than 12% of v ref ) ? latched off produced by pulling the pfcok pin above 7.5 v. generally speaking, the circuit turns off when the conditions are not proper for desired operation. in this mode, the controller stops operating. the major part of the circuit sleeps and its consumption is minimized.
NCP1612 http://onsemi.com 29 failure detection when manufacturing a power supply, elements can be accidentally shorted or improperly soldered. such failures can also happen to occur later on because of the components fatigue or excessive stress, soldering defaults or external interactions. in particular, adjacent pins of controllers can be shorted, a pin can be grounded or badly connected. such open/short situations are generally required not to cause fire, smoke nor big noise. the NCP1612 integrates functions that ease meeting this requirement. among them, we can list: ? floating feedback pins a 250 na sink current source pulls down the voltage on the feedback and fovp/buv pin so that the uvp protection trips and prevents the circuit from operating if one of this pin is floating. this current source is small (450 na maximum) so that its impact on the output regulation and ovp levels remain negligible with the resistor dividers typically used to sense the bulk voltage. ? fault of the gnd connection if the gnd pin is properly connected, the supply current drawn from the positive terminal of the v cc capacitor, flows out of the gnd pin to return to the negative terminal of the v cc capacitor. if the gnd pin is not connected, the circuit esd diodes offer another return path. the accidental non connection of the gnd pin can hence be detected by detecting that one of this esd diode is conducting. practically, the cs/zcd esd diode is monitored. if such a fault is detected for 200 s, the circuit stops operating. ? detection the cs/zcd pin improper connection the cs/zcd pin sources a 1 a current to pull up the pin voltage and hence disable the part if the pin is floating. if the cs/zcd pin is grounded, the circuit cannot monitor the zcd signal and the 200 s watchdog timer is activated. when the watchdog time has elapsed, the circuit sources a 250 a current source to pull ? up the cs/zcd pin voltage. no drive pulse is initiated until the cs/zcd pin voltage exceeds the zcd 0.75 v threshold. hence, if the pin is grounded, the circuit stops operating. circuit operation requires the pin impedance to be 3.9 k or more, the tolerance of the NCP1612 impedance testing function being considered over the ? 40 c to 125 c temperature range. ? boost or bypass diode short the NCP1612 addresses the short situations of the boost and bypass diodes (a bypass diode is generally placed between the input and output high ? voltage rails to divert this inrush current). practically, the overstress protection is implemented to detect such conditions and forces a low duty ? cycle operation until the fault is gone. refer to application note and9079/d for more details. ordering information device circuit version marking package shipping ? NCP1612adr2g NCP1612a 1612a soic ? 10 (pb ? free) 3000 / tape & reel NCP1612bdr2g NCP1612b 1612b ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP1612 http://onsemi.com 30 package dimensions soic ? 10 nb case 751bq issue a seating plane 1 5 6 10 h x 45 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.10mm total in excess of ?b? at maximum material condition. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. dimensions d and e are de- termined at datum f. 5. dimensions a and b are to be determ- ined at datum f. 6. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. d e h a1 a dim d min max 4.80 5.00 millimeters e 3.80 4.00 a 1.25 1.75 b 0.31 0.51 e 1.00 bsc a1 0.10 0.25 a3 0.17 0.25 l 0.40 1.27 m 0 8 h 5.80 6.20 c m 0.25 m dimension: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.37 ref l2 0.25 bsc a top view c 0.20 2x 5 tips a-b d c 0.10 a-b 2x c 0.10 a-b 2x e c 0.10 b 10x b c c 0.10 10x side view end view detail a 6.50 10x 1.18 10x 0.58 1.00 pitch recommended 1 l f seating plane c l2 a3 detail a d on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP1612/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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